SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 27 January 2010
39 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
[1] If the temperature sensor is not needed it should be placed in standby, which will reduce I
DD(AV)
to 0.1 糀 typical at room temperature or
3.0 糀 typical at 125 癈.
[2] High-voltage input voltage applied to pin A0 during RWP and CRWP operations. The JEDEC specification is 7 V (min.) and 10 V (max.).
When V
DD
is 3.6 V, then I
I(ov)
> 4.8 V + V
DD
or > 4.8 V + 3.6 V then the minimum voltage is 8.4 V.
Table 31. DC characteristics
V
DD
= 3.0 V to 3.6 V; T
amb
= 40 ?/SPAN>C to +125 ?/SPAN>C; unless otherwise specified. These specifications are guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD
supply voltage
3.0
-
3.6
V
I
DD(AV)
average supply current
SMBus inactive
[1]
-
210
320
糀
I
DD
supply current
f
SCL
= 400 kHz
-
250
400
糀
I
sd(VDD)
supply voltage shutdown
mode current
SMBus inactive
-
0.1
10
糀
V
IH
HIGH-level input voltage
SCL, SDA
0.7 ?V
DD
-
V
DD
+ 1
V
V
IL
LOW-level input voltage
SCL, SDA
0.5
-
+0.3 ?V
DD
V
V
I(ov)
overvoltage input voltage
pin A0; V
I(ov)
V
DD
> 4.8 V
[2]
7.0
-
10
V
V
OL
LOW-level output voltage
SDA, EVENT
I
OL
= 0.7 mA
-
-
0.2
V
I
OL
= 2.1 mA
-
-
0.4
V
I
OL
= 3.0 mA
-
-
0.5
V
V
I(hys)
hysteresis of input voltage
V
DD
e 2.2 V
0.05 ?V
DD
-
-
V
V
DD
d 2.2 V
0.10 ?V
DD
-
-
V
V
th(POR)H
HIGH-level power-on reset
threshold voltage
device operation voltage increase
-
-
2.9
V
V
th(rec)POR
power-on reset recovery
threshold voltage
device reset voltage decrease
1.2
1.8
-
V
I
LOH
HIGH-level output leakage
current
EVENT
; V
OH
= V
DD
1.0
-
+1.0
糀
I
LIH
HIGH-level input leakage
current
SDA, SCL; V
I
= V
DD
1.0
-
+1.0
糀
I
LIL
LOW-level input leakage
current
SDA, SCL; V
I
= V
SS
1.0
-
+1.0
糀
A0, A1, A2; V
I
= V
SS
1.0
-
+1.0
糀
C
i(SCL/SDA)
SCL and SDA input
capacitance
-
5
8
pF
C
i(addr)
address input capacitance
-
5
10
pF
I
pd
pull-down current
internal; A0, A1, A2 pins;
V
I
= 0.3V
DD
to V
DD
-
-
4.0
糀
Z
IL
LOW-level input impedance
pins A0, A1, A2; V
I
< 0.3V
DD
30
-
-
k?/DIV>
Z
IH
HIGH-level input impedance pins A0, A1, A2; V
I
e 0.3V
DD
800
-
-
k?/DIV>
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